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Faculty Profile


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Zarrin Tasnim Sworna

যারীন তাসনিম স্বর্ণা


Lecturer

Office Location: Room:411, Department of Computer Science and Engineering, University of Dhaka


Research Interests: Algorithm design for logic synthesis , Field programmable gate array (fpga) design, VLSI Design , Reversible computing, Human Computer Interaction


Academic


Mar 2018 - Present

Journal (2)


  1. Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu, Ashis Kumer Biswas: A Fast FPGA-Based BCD Adder.. Circuits, Systems, and Signal Processing, Springer, US. 1-25 (2018)[PDF]
  2. Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md Hasan Babu, Ashis Kumar Biswas: Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array.. IET Circuits, Devices & Systems. 10(3): 163-172 (2016)[PDF]

Conference (4)


  1. Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md Hasan Babu, Lafifa Jamal: A Cost Efficient Look-Up Table Based Binary Coded Adder Design. FTC (Future Technology Conference), IEEE, 29-30 November, 2017 in Vancouver, Canada. (2017)
  2. Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas: An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem. In VLSI (ISVLSI), 2017 IEEE Computer Society Annual Symposium on, IEEE, Bochum, Germany. 116-121 (2017)[PDF]
  3. Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md Hasan Babu: A LUT-based matrix multiplication using neural networks.. In 48th Circuits and Systems (ISCAS), 2016 IEEE International Symposium on, IEEE,Montreal, Canada. 1982-1985 (2016)
  4. Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md Hasan Babu: An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA.. In VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016 29th International Conference on, pp. . IEEE, Kolkata, India. 445-450 (2016)[PDF]